Oscillator circuit

ABSTRACT

The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV 1 -INV 5  where the output of the last CMOS inverter INV 5  is fed back to the input of the first CMOS inverter INV 1.  Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV 1 -INV 5  is formed. The first supporting transistor T 1  that helps the output of the CMOS inverter INV 5  achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T 2  that helps the output of the CMOS inverter INV 5  achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV 3  two positions ahead of the last inverter INV 5  are also formed.

CROSS-REFERENCE OF THE INVENTION

This invention is based on Japanese Patent Application No. 2003-393537,the content of which is incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an oscillator circuit, specifically to a ringoscillator circuit provided with a current mirror type current limitcircuit.

2. Description of Related Art

A ring oscillator has been used as an oscillator circuit for the variouskinds of semi-conductor integrated circuits. It is necessary to acquirea low frequency oscillator clock signal when the ring oscillator is usedas the self-refreshing oscillator circuit in a memory circuit such asDRAM. The low frequency oscillation is acquired by suppressing theelectric current of the ring oscillator using a current mirror typecurrent limit circuit.

FIG. 3 shows a ring oscillator type oscillator circuit provided with acurrent mirror type current limit circuit. In this oscillator circuit,five CMOS inverters INV1, INV2, INV3, INV4 and INV5 are seriallyconnected, and the output of the last inverter INV5 is fed back to theinput of the first inverter INV1, configuring a ring oscillator.

A current mirror type current limit circuit 10 has a P-channel type MOStransistor PM1, a resistor circuit 20 including a plurality of N-channeltype MOS transistors connected in series with a power supply voltage Vddapplied at the gate of each transistor, and an N-channel type MOStransistor NM1. The drain and the gate of the P-channel type MOStransistor PM1 are connected with each other and the source of thetransistor is provided with the power supply voltage Vdd. Also, thedrain of the P-channel type MOS transistor PM1 is connected to theresistor circuit 20. The drain and the gate of the N-channel type MOStransistor NM1 are connected with each other and the source of thetransistor is provided with the ground voltage Vss. Also, the drain ofthe N-channel type MOS transistor NM1 is connected to the resistorcircuit 20. The electric current going through the P-channel type MOStransistor PM1 and the N-channel type MOS transistor NM1 is adjusted bythe resistance of the resistor circuit 20. The resistance of theresistor circuit 20 is adjustable according to the number of theN-channel type MOS transistors serially connected.

The gate of the P-channel type MOS transistor PM1 is connected to eachgate of the P-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6that are formed at the side of the power supply voltage Vdd of each ofthe CMOS inverters. Therefore, each of the P-channel type MOStransistors PM2, PM3, PM4, PM5, and PM6 forms a current mirror with theP-channel type MOS transistor PM1 respectively, with each of theP-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6 having thesame electric current as that of the P-channel type MOS transistor PM1,which enables limiting the electric current.

The gate of the N-channel type MOS transistor NM1 is connected to eachgate of the N-channel type MOS transistors NM2, NM3, NM4, NM5, and NM6that are formed at the side of the ground voltage Vss of each of theCMOS inverters. Therefore, each of the N-channel type MOS transistorsNM2, NM3, NM4, NM5, and NM6 forms a current mirror with the N-channeltype MOS transistor NM1 respectively, with each of the N-channel typeMOS transistors NM2, NM3, NM4, NM5, and NM6 having the same electriccurrent as that of the N-channel type MOS transistor NM1, which enableslimiting the electric current.

The output of the last CMOS inverter INV5 of the ring oscillator isapplied to the gates of a P-channel type MOS transistor PM7 and anN-channel type MOS transistor NM7 of the outputting CMOS inverter INV6.The output of the CMOS inverter INV3, which is located two positionsahead of the last inverter INV5 of the ring oscillator, is applied tothe gates of a P-channel type MOS transistor PM8 and an N-channel typeMOS transistor NM8 of the same outputting CMOS inverter INV6.

The oscillation waveform is adjusted by eliminating the through currentof the CMOS inverter INV6, which is achieved by switching the P-channeltype, MOS transistor PM8 and the N-channel type MOS transistor NM8earlier than the P-channel type MOS transistor PM7 and the N-channeltype MOS transistor NM7 using the output of the CMOS inverter INV3.Furthermore, the output of the CMOS inverter INV6 is applied to theinput terminal of the CMOS inverter INV7. An oscillation clock signalRCLK is acquired from the output of the CMOS inverter INV7.

A P-channel type MOS transistor PM9 formed at the output terminal of thefirst CMOS inverter INV1 and an N-channel type MOS transistor NM9inserted to a current path of the CMOS inverter INV1 are bothtransistors for resetting controlled by a reset signal SRE.

FIGS. 4A-4C show the oscillation waveforms acquired from the circuitsimulation of the oscillator circuit described above. FIG. 4A is awaveform of the output of the CMOS inverter INV3 at a node N5, FIG. 4Bis a waveform of output of the last CMOS inverter INV5 at a node N7, andFIG. 4C is a waveform of the oscillation clock signal RCLK outputtedfrom the CMOS inverter INV7 respectively. FIG. 4A also shows the voltageat a node N1, which is a connecting point of the gates of the P-channeltype MOS transistors PM2, PM3, PM4, PM5, and PM6, as well as the voltageat a node N2, which is a connecting point of the gates the N-channeltype MOS transistors NM2, NM3, NM4, NM5, and NM6.

SUMMARY OF THE INVENTION

The invention provides an oscillator circuit that includes a ringoscillator having a plurality of inverters of an odd number. Thoseinverters are connected serially, and the output of the last inverter ofthe odd number of the inverters is fed back as an input to the first ofthe odd number of the inverters. The oscillator circuit also includes acurrent limit circuit of current mirror type controlling a currentsupplied to the odd number of the inverters, and a supporting transistorreceiving an output of one of the inverters that is located at an evennumbered position from the last inverter so as to make the output of thelast inverter swing between a power supply voltage and a referencevoltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an oscillator circuit of anembodiment of this invention.

FIGS. 2A-2C show waveforms acquired from a circuit simulation of theoscillator circuit of the embodiment.

FIG. 3 is a circuit diagram showing an oscillator circuit of prior art.

FIGS. 4A-4C show waveforms acquired from the circuit simulation of theoscillator circuit of the prior art.

FIGS. 5A-5C show waveforms acquired from the circuit simulation of theoscillator circuit of the prior art under varying conditions.

DETAILED DESCRIPTION OF THE INVENTION

The electric current going through the CMOS inverters INV1-INV5 of thering oscillator is adequately controlled by keeping the voltage of thenode N1 and the node N2 at a certain level using the current mirror typecurrent limit circuit 10 in the oscillator circuit shown in FIG. 3.However, there is a possibility that the change in a process parameteror the pattern layout deteriorates the balance of the voltage at thenode N1 and the node N2. When that happens, the balance of the drivingability between the P-channel type MOS transistors PM2-PM6 with thevoltage of the node N1 and the N-channel type MOS transistors NM2-NM6with the voltage of the node N2 also changes.

In this case, it was found that the output of the CMOS invertersINV1-INV5 forming the ring oscillator does not completely reach the LOWlevel or HIGH level. This situation gets worse as the oscillation cyclerepeats. A malfunction or a complete halt of the ring oscillator takesplace at the final stage because the output of a CMOS inverter can notexceed the threshold value of the next CMOS inverter.

FIGS. 5A-5C show the waveforms as a result of such a malfunction of theoscillation based on a simulation. FIG. 5A is a waveform of the outputof the CMOS inverter INV3 at the node N5, FIG. 5B is a waveform of theoutput of the last CMOS inverter INV5 at the node N7, and FIG. 5C is awaveform of the oscillation clock signal RCLK outputted from the CMOSinverter INV7, respectively. The impedance of the P-channel type MOStransistors PM2-PM6 becomes high, lowering the driving ability of theP-channel type MOS transistors compared to that of the N-channel typeMOS transistors NM2-NM6 when the voltage of the node N1 slightly goesup. Then, the HIGH level of the output of the inverter INV3 at the nodeN5 does not reach the power supply voltage Vdd, as shown in FIG. 5A. Thesame thing happens to the HIGH level of the output of the inverter INV5at the node N7 shown in FIG. 5B. Therefore, the oscillation clock signalRCLK stops completely as shown in FIG. 5C.

Next, an oscillator circuit of an embodiment of this invention will beexplained by referring to FIGS. 1-2C. FIG. 1 is a circuit diagram of theoscillator circuit of this embodiment. The oscillator circuit has afirst supporting transistor T1 that helps the output of the last CMOSinverter INV5 to perform the full-swing for reaching the power supplyvoltage Vdd and a second supporting transistor T2 that helps the outputof the inverter INV5 to perform the full-swing for reaching a referencevoltage, i.e., the ground voltage Vss in this embodiment, according tothe output of a CMOS inverter INV3 positioned two positions ahead of thelast CMOS inverter INV5. The other configuration of the circuit is thesame as the circuit shown in FIG. 3.

In this embodiment, the first supporting transistor TI is a P-channeltype MOS transistor, with the source provided with the power supplyvoltage Vdd, the gate with the output of the CMOS inverter INV 3, andthe drain connected to the source of a P-channel type MOS transistorPM10, to which the output of the previous CMOS inverter INV4 is applied.The source of the P-channel type MOS transistor PM10 is connected to thedrain of the P-channel type MOS transistor PM6 to form a current mirror.

The second supporting transistor T2 is, in this embodiment, an N-channeltype transistor, with the source provided with the ground voltage Vss,the gate with the output of the CMOS inverter INV3, and the drainconnected to the source of an N-channel type MOS transistor NM10, towhich the output of the previous CMOS inverter INV4 is applied. Thesource of the N-channel type MOS transistor NM10 is connected to thedrain of the N-channel type MOS transistor NM6 to form a current mirror.

Next, the operation of the oscillator circuit is explained. The balancebetween the voltage of the node N1 and the voltage of the node N2 iskept when a current mirror type current limit circuit is normallyoperated, making the ring oscillator operates normally. The node N5,which is the output of the CMOS inverter INV3, makes full-swing betweenthe power supply voltage Vdd and the ground voltage Vss, therefore thefirst and second supporting transistors T1 and T2 do not have any effecton the operation of the ring oscillator.

Next, the operation of the oscillator circuit when the voltage of thenode N1 slightly goes up due to changes in a process parameter or thepattern layout will be explained by referring to the simulation waveformshown in FIGS. 2A-2C. The impedance of the P-channel type MOStransistors PM2-PM6 becomes high, lowering the driving ability of theP-channel type MOS transistors PM2-PM6 compared to that of the N-channeltype MOS transistors NM2-NM6. Therefore, the HIGH level of the node N5,the output of the inverter INV3 does not reach the power supply voltageVdd as shown in the waveform of the FIG. 2A.

However, the first supporting transistor T1 turns on by receiving theoutput of the node N5 that is not high enough for the HIGH level in theoscillator circuit of this invention. Then, the power supply voltage Vddis fed to the P-channel type MOS transistor PM10 of the CMOS inverterINV5 with a low impedance. Therefore, the node N7, the output of theCMOS inverter INV5 makes the full-swing between the power supply voltageVdd and the ground voltage Vss, as shown in FIG. 2B. The normaloscillation clock signal RCLK can be acquired from the CMOS inverterINV7 as shown in FIG. 2C.

Next, the operation of the oscillator circuit when the voltage of thenode N2 slightly goes down due to changes in the process parameter orthe pattern layout will be explained. The impedance of the N-channel MOStransistors NM2-NM6 becomes high, lowering the driving ability of theN-channel type MOS transistors NM2-NM6 compared to that of the P-channeltype MOS transistors PM2-PM6. Therefore, the LOW level of the node N5,the output of the inverter INV3 does not go down to the ground voltageVss.

However, the second supporting transistor T2 turns on by receiving theoutput of the node N5 that is not low enough for the LOW level in theoscillator circuit. Then, the ground voltage Vss is fed to the N-channeltype MOS transistor NM10 of the CMOS inverter INV5 with a low impedance.Therefore, the node N7, the output of the CMOS inverter INV5 makes thefull-swing between the power supply voltage Vdd and the ground voltageVss. The normal oscillation signal RCLK can be acquired from the CMOSinverter INV7.

There are five CMOS inverters that form the ring oscillator in the aboveembodiment of this invention. However, this invention is not limited tothis embodiment. The ring oscillator may be configured with the CMOSinverters in odd numbers three and above. Also, the output of the CMOSinverter INV3, which is two positions ahead of the last CMOS inverterINV5, is applied to the gates of the first and the second supportingtransistors T1 and T2 in the above embodiment. However, otherconfiguration is also possible. In general, it is possible to apply theoutput of the CMOS inverter located at even-numbered positions (thesecond position, the fourth position, and so on) counting from the lastinverter.

According to this embodiment, the malfunction and the halt of the ringoscillator circuit due to the imbalance of the current mirror caused bychanges in a process parameter or the pattern layout can be prevented inthe ring oscillator circuit with the current mirror type current limitcircuit.

1. An oscillator circuit comprising: a ring oscillator comprising aplurality of inverters of an odd number, the inverters being connectedserially, and an output of the last inverter of the odd number of theinverters being fed back as an input to the first of the odd number ofthe inverters; a current limit circuit of current mirror typecontrolling a current supplied to the odd number of the inverters; and asupporting transistor receiving an output of one of the inverters thatis located at an even numbered position from the last inverter so as tomake the output of the last inverter swing between a power supplyvoltage and a reference voltage.
 2. The oscillator circuit of claim 1,wherein the supporting transistor comprises a first P-channel type MOStransistor.
 3. The oscillator circuit of claim 2, wherein the output ofthe inverter located at the even-numbered position is applied to a gateof the first P-channel type MOS transistor, the power supply voltage isapplied to a source of the first P-channel type MOS transistor, and adrain of the first P-channel type MOS transistor is connected to asource of a second P-channel type MOS transistor that is part of thelast inverter.
 4. The oscillator circuit of claim 1, wherein thesupporting transistor comprises a first N-channel type MOS transistor.5. The oscillator circuit of claim 4, wherein the output of the inverterlocated at the even-numbered position is applied to a gate of the firstN-channel type MOS transistor, the reference voltage is applied to asource of the first N-channel type MOS transistor, and a drain of thefirst N-channel type MOS transistor is connected to a source of a secondN-channel type MOS transistor that is part of the last inverter.
 6. Anoscillator circuit comprising: a ring oscillator comprising a pluralityof inverters of an odd number, the inverters being connected serially,and an output of the last inverter of the odd number of the invertersbeing fed back as an input to the first of the odd number of theinverters; a current limit circuit of current mirror type controlling acurrent supplied to the odd number of the inverters; a first P-channeltype MOS transistor; and a first N-channel type MOS transistor, whereinan output of one of the inverters that is located at an even-numberedposition from the last inverter is applied to a gate of the firstP-channel type MOS transistor, a power supply voltage is applied to asource of the first P-channel type MOS transistor, and a drain of thefirst P-channel type MOS transistor is connected to a source of a secondP-channel type MOS transistor that is part of the last inverter, and theoutput of the inverter located at the even-numbered position is appliedto a gate of the first N-channel type MOS transistor, a referencevoltage is applied to a source of the first N-channel type MOStransistor, and a drain of the first N-channel type MOS transistor isconnected to a source of a second N-channel type MOS transistor that ispart of the last inverter.